1. Technical Field
The present invention relates to a high frequency switch circuit built in a switch semiconductor integrated circuit or a communication terminal device. In particular, the invention is preferably applicable in a high frequency switch circuit which needs to have low insertion loss, high isolation, and low distortion characteristics, as well as in a communication terminal device using this switch circuit. This high frequency switch circuit is used, for example, as an antenna switch in a portable phone.
2. Prior Art
In these days, mobile telecommunication business such as in car telephones and portable phones is growing in remarkable rapidness. In many countries in the world, various mobile telecommunication systems have commenced operations. Meanwhile, in these mobile telecommunication systems, semiconductor field effect transistors (FETs) are used widely in signal processing units in major portable terminals. In particular, in order to improve the portability in portable terminals, considerable efforts are devoted into the development of monolithic microwave ICs (MMICs) using GaAs-FETs which are expected to serve as semiconductor integrated circuit devices permitting all of size reduction, low voltage driving, and power consumption reduction. Among these MMICs, high frequency switches for switching a high frequency signal in a portable terminal are important as a target of development.
When an FET is used as a switching device, a bias voltage applied to the gate terminal of the FET needs to be controlled. For example, when a gate bias sufficiently higher than the pinch-off voltage is applied to the gate terminal, the drain-source impedance is reduced, so that the FET is controlled to go ON. On the contrary, when a gate bias sufficiently lower than the pinch-off voltage is applied to the gate terminal, the drain-source impedance is increased, so that the FET is controlled to go OFF.
When such a single FET is used as a switching device, a GaAs-FET has a low insertion loss, but has a difficulty in increasing the isolation. The isolation in a single FET is increased by reducing the gate width of the FET. Nevertheless, the reduction of the gate width causes an increase in the ON resistance, and hence causes the problem of an increase in the insertion loss. Thus, a low insertion loss and a high isolation are difficult to be achieved simultaneously.
As such, a low insertion loss and a high isolation are difficult to be achieved simultaneously in a single FET. However, this problem is addressed by using a combination of FETs.
An example of a high frequency switch circuit having such configuration is an SPDT (single pole dual throw) switch composed of a series FET and a shunt FET connected respectively in series and in shunt relative to the signal path (for example, see JP-A-H08-213893 (pp. 2–3 and FIG. 2)). The series FET is an FET connected in an inserted configuration into the signal line. The shunt FET is an FET connected between the signal line and the ground.
According to this configuration, an RF signal having been leaked through a parasitic capacitance component in the series FET in an OFF state is drawn into the ground via the shunt FET in an ON state. This realizes a high isolation.
Further, this single stage FET circuit composed of one series FET and one shunt FET for reducing the signal leakage through the series FET in the OFF state may be duplicated into a cascade of multistage. This configuration further reduces the signal leakage through this single stage FET circuit.
Nevertheless, in the configuration of such a multistage cascade of the FET circuits, the voltage is undetermined in the intermediate connection points between a plurality of these series FETs. This causes instability in the operation of the series FETs, and hence prevents reliable ON-OFF switching based on the gate voltage control.
In order to resolve this problem, a modification is proposed that in the multistage cascade of the FET circuits, the source and the drain of each FET are interconnected through a resistor (for example, see JP-A-2000-277703 (pp. 4–5 and FIG. 1)). This configuration is shown in FIG. 9. In FIG. 9, numerals 111–114 indicate FETs interconnected in series. Numerals 211–214 indicate resistors one end of each of which is connected to the gate of each FET 111–114. Numerals 215–218 indicate resistors each of which interconnects the source and the drain of each FET 111–114. Numerals 311 and 312 indicate high frequency signal input and output terminals. Numeral 411 indicates a control terminal connected in common to the other terminals of the resistors 211–214 so as to receive a control signal for controlling the ON-OFF of the FETs 111–114.
As such, in this configuration, the source and the drain of each FET 111–114 are interconnected through each resistor 215–218, so that the voltage is fixed at the intermediate connection points between a plurality of the series FETs 111–114. This stabilizes the operation of the FETs.
In this configuration of the prior art, in the multistage cascade of the FET circuits, the voltage is fixed at the intermediate connection points between the FETs. Never the less, this voltage has a value arbitrarily determined by the gate voltage of the FET as well as the gate-source resistance Rgs and the gate-drain resistance Rgd of the FET.
When the FETs are to be set OFF by an arbitrary voltage, the gate voltage is changed, and so is the voltage in the intermediate connection points. This can result in a situation that the signal inputted through the high frequency signal input and output terminal 311 or the other is not shut off reliably. In particular, when a large signal is inputted, the FETs cannot reliably be set OFF, so that the signal can leak.
Described below is the reason why the FETs cannot reliably be set OFF when a large signal is inputted. When a high frequency signal is inputted to the high frequency switch circuit composed of the FETs, the voltage amplitude depends on the input power. When a signal of a high power is inputted, the voltage amplitude becomes accordingly large. This results in a situation that at the timing near the peak of the high frequency voltage waveform, the gate-source voltage of the FETs cannot be maintained in a reverse bias state. This causes temporary conduction in the FETs near the peak of the high frequency voltage waveform. This mechanism is described in detail in JP-A-H07-106937.
For example, when FETs are used in an antenna switch, the highest priority is assigned to the reduction of the insertion loss. The reduction of the insertion loss requires the reduction of the ON resistance of the FETs. When the FETs are used in a forward bias state, the ON resistance of the FETs can be reduced. Nevertheless, in the above-mentioned configuration of the prior art, the voltage of the intermediate connection points is arbitrarily determined as described above. This has prevented the high frequency switch circuit from being used in a state of the lowest ON resistance.